`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   19:35:15 04/05/2013
// Design Name:   sev_seg_disp
// Module Name:   C:/Users/Taylor/Documents/CSE 320/Lab2/Lab2/tb_sev_seg_disp.v
// Project Name:  Lab2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: sev_seg_disp
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_sev_seg_disp;

	// Inputs
	reg [7:0] read_data;
	reg rst;
	reg clk_50mhz;

	// Outputs
	wire data_displayed;
	wire [3:0] dis_control;
	wire [6:0] led_dis;

	// Instantiate the Unit Under Test (UUT)
	sev_seg_disp uut (
		.read_data(read_data), 
		.rst(rst), 
		.clk_50mhz(clk_50mhz), 
		.data_displayed(data_displayed), 
		.led_dis(led_dis),
		.dis_control(dis_control)
	);

	initial begin
		// Initialize Inputs
		read_data = 0;
		rst = 1;
		clk_50mhz = 0;

		// Wait 100 ns for global reset to finish
		#10;
        
		// Add stimulus here
		forever #5 clk_50mhz <= ~clk_50mhz;

	end
	
	initial begin
	
		// CASE 1 (no read_data)
		#10 rst <= 0;
		#5 rst <= 1;
		#440;
		
		// CASE 2
		#10 rst <= 0;
		#5 rst <= 1;
		read_data <= 8'b0x11111111;
		#350;	// wait until 
		
		// CASE 3
		read_data = 8'b0x10100100;
		#350;
		
		// CASE 4
		read_data = 8'b0x11010110;
		#250 rst <= 0;
		#50 rst <= 1;
		#40 read_data <= 8'b0x10111100;
		#10;
		
		// Case 5
		
	end
      
endmodule

